1. Field of the Invention
The present invention relates to semiconductor devices and, more particularly, complementary metal-oxide semiconductor (CMOS) devices which operate at cryogenic temperatures and which are radiation hard.
2. Description of Related Art
Complementary metal-oxide semiconductor (CMOS) technology is so named because it uses both p- and n-type (i.e., complementary) metal-oxide semiconductor (MOS) transistors in its circuits. CMOS has its origins in 1963, and the first CMOS integrated circuits (ICs) were fabricated in 1966. The earliest commercial application in volume was in digital watches in which power consumption is a primary concern. Later, CMOS was widely used in circuits for calculators in which low-power dissipation is important, and in circuits where very high noise margins are important, e.g., radiation-hard circuits.
With the dawning of the very large-scale integration (VLSI) era, power consumption in conventional n-type metal-oxide semiconductor (NMOS) circuits began to exceed tolerable limits. A lower power technology was needed to exploit the VLSI fabrication techniques. CMOS represented such a technology.
From 1968 to 1987, a 200-fold increase in functional density and a 20-fold increase in speed of integrated circuits took place. One example of this tremendous increase in density is the Intel 4004 4-bit microprocessor which in 1971 had 2,300 devices. By 1995, the well-known Intel 80386 16-bit processor had 275,000 devices.
Although CMOS has many advantages, CMOS is susceptible to short-channel and hot-carrier effects when device channel lengths drop below about 2 .mu.m. In addition, hot-electron effects in n-channel devices typically become more severe as channel lengths narrow. In addition, well contacts must be provided in CMOS circuits, which take up more chip area than in other IC technologies.
One application for CMOS devices is in focal plane array (FPA) technology. Focal plane arrays are used in night-vision devices which thermally image scenes using infrared radiation. The focal plane arrays are cooled to cryogenic temperatures in order to reduced unwanted thermal noise. Hence, the category of CMOS devices used at cryogenic temperatures is known as cryo-CMOS.
Current FPA processes require channel stops around each n-channel device for low-temperature radiation-hardening purposes. This process is not self-aligned and requires a large space between the channel stop and n+ implantation region. The active-area region is defined by a wet chemical oxide etch process and not by a local oxidation process (LOCOS) currently widely used in the IC industry.
Many applications in focal plane array technologies require radiation-hard, high-density, large-array read-outs. To do this, high-density, low-noise, and radiation-hard cryo-CMOS processes are required. Current FPA processes yield channel lengths in the neighborhood of 4 micrometers (.mu.m). Reducing the channel length further presents many difficulties.
Conventional fabrication processes may yield a minimum channel length of 2.5 .mu.m, which is usually the smallest achievable for these processes. Many new applications require device channel length to be in the submicron range (i.e., less than 1 .mu.m) to increase device speed, packing density, and read-out resolution while maintaining the same low-temperature radiation hardness and device performance.
Accordingly, it is an object of the present invention to provide a process which produces a radiation-hard cryo-CMOS device with channel lengths in the submicron region without experiencing any degradation in device radiation hardness or in device performance.